P-doped material is commonly used as a substrate upon which integrated circuits and other semiconductor devices are formed. The P-type substrate is commonly tied to ground. Particular integrated circuit designs, however, allow for the P-type substrate to be negatively biased. An example of such an integrated circuit design is a TFT-LCD (Thin Film Transistor, Liquid Crystal Display) driver integrated circuit. Various design rule restrictions apply for negatively biased P-type substrates depending on the particular technology used. Examples of such a technology are triple gate technologies that use at least one high voltage and a plurality of low voltages. Low voltage devices with different potentials must be isolated using individual dedicated N+ buried layers (NBL) combined with high voltage N-well (HVNW) areas, that is, low voltage devices with different voltage potentials must not be connected to a common NBL using conventional technology. N+ buried layers are required for high voltage PMOS and isolated high voltage NMOS devices. If LVNW areas of different potentials contact a common NBL, then the subsequent thermal processing utilized in device formation will cause a diffusion of impurities from the common NBL into each of the low voltage N-well areas. In this case, the LVNW areas will be coupled to each other through the NBL preventing the respective low voltage N-well areas from being biased at different potentials. Therefore, using conventional technology, low voltage N-well areas desired to be biased at different potentials must be individually separated from the substrate by an associated NBL in combination with a high voltage N-well (HVNW) area. LVNW areas are conventionally formed over the NBL meaning that a plurality of individually dedicated NBL's would be required to correspond to the superjacent LVNW areas that are to be biased differently. Design rules typically require that adjacent NBL areas include a minimum spacing of about 12 microns or thereabout. Therefore, the approach of forming a corresponding NBL in a substrate for each low voltage N-well area to accommodate the low voltage N-well areas being biased differently, is not favored because the formation of so many NBL areas would necessarily and significantly enlarge chip size undesirably.
It would therefore be advantageous to form a plurality of low voltage N-well areas that can be bias at different potentials, over a common NBL.